PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 157
15.1
Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 15-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 15-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 15-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 15-2. It may be advantageous to use
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
15.1.1
OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
15.1.2
SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 15-1:
BAUD RATE FORMULAS
EXAMPLE 15-1:
CALCULATING BAUD RATE ERROR
TABLE 15-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
00
0
8-bit/Asynchronous
FOSC/[64 (n + 1)]
00
1
8-bit/Asynchronous
FOSC/[16 (n + 1)]
01
0
16-bit/Asynchronous
01
1
16-bit/Asynchronous
FOSC/[4 (n + 1)]
10
x
8-bit/Synchronous
11
x
16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
SPBRGH
EUSART Baud Rate Generator Register High Byte
SPBRG
EUSART Baud Rate Generator Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate
=
FOSC/(64 ([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
X
=
((FOSC/Desired Baud Rate)/64) – 1
=
((16000000/9600)/64) – 1
=
[25.042] = 25
Calculated Baud Rate
=
16000000/(64 (25 + 1))
=
9615
Error
=
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
=
(9615 – 9600)/9600 = 0.16%
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